1. Field of the Invention
The present invention relates to a semiconductor storage device, and in particular to a defect relief technique effectively applicable to a dynamic RAM (random access memory) having a large storage capacity.
2. Description of the Related Art
In the case where a faulty address storage and an address comparator are provided for each redundant word line as a defect relief technique for a semiconductor storage device, an increased number of fuse circuits are undesirably required for storing faulty addresses corresponding to the respective redundant word lines. With a technique developed in an effort to overcome this disadvantage, a set of fuses is provided for a plurality of word lines. Such a plurality of word lines including a faulty word line are collectively switched to redundant word lines. With this configuration, therefore, a plurality of word lines are switched at a time. In this way, regardless of whether a fault occurs in a single or a plurality of word lines, the faults can be relieved by the fuse circuit. The overall relief efficiency, therefore, is improved.
Conventional techniques related to the present application are disclosed in JP-A-2-158995 and JP-A-61-20293.